1. Field of the Invention
The present invention relates to a semiconductor memory device and a manufacturing method of the same, more particularly to a dynamic random access memory(hereinafter referred to as a DRAM) of a capacitor-over-bit-line type (referred to as COB type) in which a stacked type capacitor is arranged at a position higher than bit lines and a manufacturing method of the same.
2. Description of the Related Art
In the DRAM in which a memory cell consists of one transistor and one capacitor, an objective in developing the DRAM is to satisfy simultaneously a reduction in memory cell size and a reduction in memory cell capacitance in each memory cell with a good controllability, for requirements for a large capacitance of the DRAM. Reflecting in such technological trend, recent years, the DRAM having the stacked type capacitance has been mainly used. Furthermore, there has been a trend to increase an effective surface area of a storage node electrode, which is a member of the capacitor, per unit projection area by devising shapes of the storage node electrode three-dimensional. Corresponding to these trends, the COB type DRAM is coming to be mainly used. The adoption of the COB type DRAM offers such constitution that the storage node electrode, which has been arranged lower than the bit lines, is located at a position higher than the bit lines. Therefore, this facilitates to give a three dimensional shape to the storage node electrode.
When the descriptions for various proposals concerning the three dimensional shape of the storage node electrode are omitted, the structure of the conventional COB type DRAM having the stacked type capacitor will be summarized as follows.
In a region where memory cell arrays are formed in a surface of a P type silicon substrate, a plurality of element formation regions are arranged regularly which are defined by field oxide films. One word line traverses a plurality of the element formation regions interposing gate oxide films. The word lines are arranged in parallel in a Y-direction. In each of the element formation regions, at least one MOS transistor is formed which consists of a gate electrode formed of the word line, and N and N type source and drain regions which are formed in a surface of a P type silicon substrate in self-aligned with the word line. The surface of the P type substrate as well as the word lines is covered with a first underlayer insulating film. A bit contact hole reaching the N type drain region is formed in the first underlayer insulating film. A plurality of bit lines formed which are formed in parallel in a X-direction perpendicular to the Y-direction on the surface of the first underlayer insulating film are connected to the corresponding N type drain regions through the bit contact holes. The bit lines are arranged so as not to pass just above the N type source regions. The first underlayer insulating film as well as the bit lines is covered with a second underlayer insulating film.
Node contact holes, each of which penetrates the first and second underlayer insulating films and reaches the corresponding N type source region, are arranged at positions where the bit lines are not present. A capacitor consists of a cell plate electrode, a capacitive insulating film, and a storage node electrode connected to the corresponding N type source region. The storage node electrode connected to the N type source region through the node contact hole has a shape that it covers directly the surface of the second underlayer insulating film near the respective node contact hole. The capacitive insulating film covers directly a portion other than the portion of the surface of the second underlayer insulating film where the memory cell array is formed, the portion of the surface of the second underlayer insulating film being covered directly by the storage node electrode. The capacitive insulating film covers directly also a portion other than the portion of the surface of the storage node electrode which covers directly the node contact hole and the second underlayer insulating film. The cell plate electrode covers directly the entire surface of the capacitive insulating film positioned in the side which is not in contact with the second underlayer insulating film and the storage node electrode.
In the memory cell of the conventional COB type DRAM having the stacked type capacitor, to increase the capacitance value per projection area unit, the three-dimensional shape of the storage node electrode has been principally devised. As long as there is a restriction that each of the cell plate and the capacitive insulating film constituting the capacitor is formed of a sheet of a almost continuous film, the means to achieve an increase in the capacitance value is restricted only to the device of the shape of the storage node electrode. Whenever the present capacitive insulating film and cell plate are employed, of the portion of the surface of the storage node electrode, the portion other than the portion in which the node contact hole and the second underlayer insulating film are covered by the storage node electrode does not contribute to the formation of the capacitor.